(1) Field of the Invention
The present invention relates to a phase-comparison bit synchronizing circuit for establishing bit phase synchronization of signals transmitted by way of TDMA (Time-Division Multiplex Access), and more particularly to a phase-comparison bit synchronizing circuit in a receives for receiving, over a single optical fiber transmission path, bursts of signals transmitted from a plurality of subscribers.
(2) Description of the Related Art
There have been plans in recent years to give telephone subscribers highly sophisticated services such as for providing multimedia information.
Such highly sophisticated services involve a vast amount of information to be transmitted to the telephone subscribers. Since such a vast amount of information cannot be handled by conventional metallic telephone wires, it is necessary to construct subscriber lines of optical fibers.
One of the networks available for subscriber lines of optical fibers is a passive optical network (PON) as shown in FIG. 6 of the accompanying drawings. As shown in FIG. 6, a single optical fiber (main track) 102 from a central telephone office 101 is branched by an optical coupler 103 into a plurality of optical fibers (branch lines) 104.about.109 that are connected to respective subscriber's homes 110.about.115. The PON allows subscriber's homes scattered in a wide area to be economically and efficiently accommodated with a few optical fibers (main tracks) from the central telephone office.
The PON employs a TDMA process, for example, for upstream communications from the subscriber's homes 110.about.115 to the central telephone office 101. According to the TDMA process, burst signals are transmitted at predetermined different times respectively from the subscriber's homes 110.about.115 to the central telephone office 101, such that the burst signals from respective subscribers 1, 2, 3, 4, . . . are arranged without being superposed in each frame for time-division multiplexing as shown in FIG. 7 of the accompanying drawings. The central telephone office 101 receives frames of multiplexed signals, and determines from which subscriber each of the burst signals is transmitted based on the sequence of the burst signals. The sequence of the burst signals remains unchanged in the frames.
The signals transmitted from the subscriber's homes 110.about.115 are held in synchronism with downstream signals from the central telephone office 101. Therefore, frequency synchronization is basically established in the receiving circuit in the central telephone office 101. Since the lengths of the optical fibers (branch lines) 104.about.109 are different from each other because of the different locations of the subscriber's homes 110.about.115, the burst signals transmitted from the subscriber's homes 110.about.115 to the central telephone office 101 are out of bit phase with each other. Consequently, the receiving circuit in the central telephone office 101 is required to establish bit phase synchronization of each of the burst signals.
Using a bit synchronizing circuit for each of the burst signals is not practical because as many bit synchronizing circuits would be required as the number of subscribers. One solution is to use a phase-comparison bit synchronizing circuit.
As shown in FIG. 8 of the accompanying drawings, a phase-comparison bit synchronizing circuit shifts the bit phases of the burst signals from the subscribers 1, 2, 3, . . . with delay elements or the like, so that the burst signals are stably synchronized with a bit clock signal in the receiving circuit. Stated otherwise, the bit phases of the burst signals are adjusted individually in order to align the central positions of the bits of the burst signals with respective positive-going edges of the bit clock signal in the receiving circuit. In this manner, the bit data of the burst signals can be reproduced. While the burst signals are shown as being composed of several bits in FIG. 8 for illustrative purpose, they are actually composed of several tens to several thousands bits.
The arrangement of a conventional phase-comparison bit synchronizing circuit will be described below with reference to FIG. 9 of the accompanying drawings. Signals in the conventional phase-comparison bit synchronizing circuit are shown in FIG. 10 of the accompanying drawings, and which will be referred to in the description given below.
A given burst signal that is transmitted from the subscriber 1 indicated at 1 in FIG. 10 is supplied successively to seven series-connected delay elements (DL) 121.about.127 of the conventional phase-comparison bit synchronizing circuit. The delay time of each of the delay elements 121.about.127 is one-eighth of the period of the bit clock signal in the receiving circuit. The given burst signal itself and delayed signals from the delay elements 121.about.127, which are shifted in phase from the given burst signal, are then supplied to the respective D terminals of a D flip-flop (F/F) 128. The signals supplied to the respective D terminals of the D flip-flop 128 are indicated respectively by 1-a.about.1-h in FIG. 10. The D flip-flop 128 has a clock terminal supplied with the bit clock signal in the receiving circuit. The bit clock signal is indicated by 2 in FIG. 10. As indicated by 1 in FIG. 10, the burst signal from each of the subscribers comprises three areas, i.e. , a preamble (PR), a frame (FR), and data. The pressable (PR) is composed of a sequence of bits "1, 0", and used to establish bit phase synchronization and adjust the amplification factor of a receiving amplifier. The frame (FR) is used to establish frame synchronization of the burst signal.
The D flip-flop 128 synchronizes the signals supplied respectively to the D terminals thereof with positive-going edges of the bit clock signal supplied to the clock terminal thereof, and output signals indicated by 3-a.about.3-h in FIG. 10. Specifically, the D flip-flop 128 outputs the signals supplied respectively to the D terminals thereof at the times of the positive-going edges of the bit clock signal, and keeps the outputted signals until the next positive-going edges of the bit clock signal.
A phase comparator 129 compares the output signals from the D flip-flop 128, i.e., compares adjacent ones of the signals indicated by 3-a.about.3-h in FIG. 10 in the indicated sequence to detect signals whose data has changed. In the example shown in FIG. 10, a data change occurs between the signals 3-a, 3-b, and also between the signals 3-e, 3-f. These signals whose data has changed are considered to have a minimum margin when they are synchronized with the bit clock signal in the receiving circuit. The phase comparator 129 selects signal which is 180.degree. out of phase with these signals, i.e., a signal whose setup, hold margins are largest with respect to the bit clock signal. In the example shown in FIG. 10, the phase comparator 129 selects the signal 3-c or 3-d or the signal or 3-h. The phase comparator 129 supplies a selector (SEL) 130 with an input terminal signal which is a coded representation of any one of input terminals of the selector 130 to which the signal selected by the phase comparator 129 is applied.
The input terminals of the selector 130 are supplied with the respective output signals from the D flip-flop 128. The selector 130 selects only the signal applied to the input terminal thereof which is indicated by the input terminal signal that is supplied from the phase comparator 129, and supplies the selected signal to the D terminal of a D flip-flop (F/F) 131. The D flip-flop 131 shapes the waveform of the signal supplied to the D terminal thereof based on the bit clock signal that is supplied to a clock terminal thereof, and outputs the shaped waveform as bit reproduced data.
The conventional phase-comparison bit synchronizing circuit of the above arrangement adjusts the phase of a burst signal while its preamble (PR) is being inputted so that the burst signal can stably be synchronized with the bit clock signal in the receiving circuit. The frame (FR) and data of a succeeding burst signal also pass through the selected delay element. Therefore, the frame (FR) and the data are also adjusted in phase, and are stably synchronized with the bit clock signal in the receiving circuit.
Each time a new burst signal, i.e., a burst signal from another subscriber such as the subscriber 2 as indicated at 1 in FIG. 10, is inputted, the conventional phase-comparison bit synchronizing circuit selects the amount of a new phase shift to be made. Even when a next frame is reached and the burst signal from the subscriber 1 is inputted, the conventional phase-comparison bit synchronizing circuit selects the amount of a new phase shift to be made.
The conventional phase-comparison bit synchronizing circuit is arranged to determine the amount of a new phase shift to be made for phase adjustment each time a burst signal is inputted in each frame from the same subscriber.
The amount of a phase shift is determined in relation to the length of the branch line of each subscriber. Therefore, the amount of a phase shift to be made with respect to burst signals from the same subscriber does not basically vary in each frame, and hence may not be determined each time a burst signal is inputted from the same subscriber.
If the amount of a phase shift to be made is determined each time a burst signal is inputted from the same subscriber and the determined amount varies, then the preamble of the burst signal is considered to suffer a problem due to disturbance. When phase adjustment is made based on such a wrong amount of a phase shift, burst signals may not be synchronized in appropriate bit phase, and may have different data error rates.